Semiconductor packages are commonly utilized in integrated circuit applications. One common semiconductor device package arrangement includes a substrate that acts as a heat sink and lid that can be placed over the substrate so as to form an internal cavity over the substrate. Integrated circuits, such as semiconductor chips, as well as other electrical components, may be placed within the cavity and electrically connected to conductive leads that extend out from the base. The conductive leads enable electrical connection between the package and a receptacle, such as a printed circuit board. Thus, the packaged arrangement allows for easy electrical connection between the circuits to external devices while simultaneously protecting the semiconductor chip and electrical connections from damaging environmental conditions, such as moisture, particles, etc.
Package designers are constantly seeking to improve packaging designs. One notable design consideration is the total footprint of the package. Reducing the total footprint of the package may beneficially reduce the size and/or cost of the item incorporating the packaged device. Two parameters that substantially influence the total footprint of the package are the size of the substrate and the size of the leads. That is, one can reduce the total footprint of the package by reducing the size of these features. However, reducing the size of these features introduces further design complications. The substrate must maintain a sufficient size to accommodate the die area of the semiconductor devices. Further, the leads must maintain a sufficient cross-sectional area to accommodate the electrical currents associated with the packaged electrical devices. Thus, the physical and electrical requirements of the packaged devices inhibit the ability to reduce the total footprint of the package.